1. Technical Field of the Invention
The present invention relates to memory devices, and more particularly to a fast memory sense system for sensing data stored in a memory array.
2. Description of the Related Art
A memory array generally comprises a plurality of memory cells arranged in rows and columns, where each cell stores a corresponding data bit. Memory cells in each row are enabled by a corresponding word line signal asserted on a corresponding word line by an array of word line drivers. Usually, only one of the word line signals for the memory array is asserted at a time. An address is provided to a word line decoder which decodes the address and asserts one of the word line signals. Each column of memory cells is connected to a complementary pair of bit line signals. Thus, the enabled memory cell in each column drives a corresponding bit line and a complementary bit line forming the pair of complementary bit lines. A row of sense amplifiers typically runs along the bottom of the memory array, where each sense amplifier senses the enabled memory cell for accessing the corresponding data bit. A corresponding array of output latches are coupled to the array of sense amplifiers for latching the output data during a memory access.
Typical memory architectures enabled the sense amplifiers as soon as possible and were designed with the "low to high" and "high to low" access times as equal as possible. In this manner, each amplifier was symmetrical and optimized for equal slew in either direction to read either a low or a high bit. In some designs, the sense amplifiers were not enabled until after a known differential was asserted on the bit lines. Once enabled, the sense amplifiers initialized into the correct state. However, this required an inherent delay to assure reliable data, since an adequate differential had to first be developed between the bit lines before the amplifiers were activated. Thus, either of these methods resulted in less than an optimal design having minimal time delays.
It is desired to minimize the time to retrieve data from the cells of a memory array while maintaining data integrity.